Dynamic random access memory (DRAM) may be utilized for storing information in programmable systems. DRAM may be fabricated in an array comprising individual memory cells containing a transistor in combination with a programmable device. In some applications, the programmable device may be a charge-storage device (such as, for example, a capacitor). Bitlines (i.e., digit lines) and wordlines (i.e., access lines) may extend across the array, and may be utilized for accessing individual memory cells.
A continuing goal is to increase integration, and accordingly to increase packing density of DRAM and other circuitry. An example memory array architecture 10 is described with reference to FIG. 1, and in some applications such memory array architecture may be utilized to achieve high-density packing.
The architecture 10 includes wordlines WL1, WL2 and WL3 extending along a first direction of an axis 5; and includes bitlines BL1, BL2 and BL3 extending along a second direction of an axis 7; with the second direction crossing the first direction. The wordlines may be considered to extend along rows of the memory array architecture, and the bitlines may be considered to extend along columns of the memory architecture.
Active material structures 12 are within the architecture 10, and are provided at intersections of the wordlines and bitlines. The active material structures 12 may comprise pillars of monocrystalline silicon, and may be generally shaped as parallelograms (as shown). The active material structures are provided in dashed-line view to indicate that they may be beneath other materials relative to the top view of FIG. 1.
Each of the active material structures 12 has a bit contact region BC and a cell contact region CC, with the bit contact regions being on opposing sides of the active material structures relative to the cell contact regions.
The bit contact regions BC are coupled with the bitlines BL1, BL2 and BL3; and the cell contact regions CC are coupled with programmable devices 14 (e.g., charge-storage structures, such as, for example, capacitors).
The memory array architecture 10 of FIG. 1 may be analogous to architecture described in U.S. Pat. No. 9,472,542, which is assigned to Micron Technology, Inc., and which lists Wolfgang Mueller and Sanh D. Tang as inventors.
A problem with the architecture 10 of FIG. 1 is that it may be difficult to couple the bitlines BL1, BL2 and BL3 with the bit contact regions BC and/or to couple the programmable devices 14 with the cell contact regions CC due to the tight packing of such architecture. Specifically, there are very small regions of the active material structures 12 available for making connection to the bitlines and the programmable devices. Such problem may become more severe as corners of the active material structures 12 are rounded in accordance with particular embodiments described in U.S. Pat. No. 9,472,542. Accordingly, it is desired to develop improved architectures which enable better connection between bit contact regions and bitlines, and/or which enable better connection between cell contact regions and programmable devices.